1. Field of the Invention
The invention relates to electronic memory devices, and more particularly, to self-aligned split-gate memory cells with stacked control gate structures and fabrication methods thereof.
2. Description of the Related Art
Nonvolatile memory, including electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM, is currently available in several forms for retaining stored data during periods when no power is applied. Conventionally, non-volatile memory comprises stacked gate and split gate cell structures. The stacked gate memory cells normally have a floating gate and a control gate, with the control gate positioned directly above the floating gate. In a split-gate memory cell, the control gate, while positioned above the floating gate, is laterally offset therefrom. A split-gate memory cell normally includes an additional gate known as a select gate which involves relatively complex processing steps.
In the manufacture of a split-gate memory cell, the floating gate pattern is commonly formed with one photolithographic mask, and the control gate or select gate pattern is then defined with another. U.S. Pat. Nos. 6,091,104 and 6,291,297, the entirety of which is hereby incorporated by reference, disclose a split-gate memory cell of relatively small size, efficient erasure performance, and relatively small programmable current requirements. The small size is obtained through self-alignment of the select, control and floating gates and the efficiency in erasure is provided by the use of Fowler-Nordheim tunneling from a sharply rounded side edge of the floating gate to the select gate. The programming current is kept small by the use of mid-channel hot carrier injection from the off-gate channel region between the select gate and the floating gate to the sharply curved side edge of the floating gate.
Flash memory cells with separated self-aligned select and erase gates are also disclosed in, for example, U.S. Pat. No. 6,747,310, the entirety of which is hereby incorporated by reference. FIG. 1A is a cross-section of a conventional self-aligned split-gate NOR-type flash memory cell, taken along line 2-2 in FIG. 1B. FIG. 1B is a plan view of the conventional self-aligned split-gate NOR-type flash memory cell. Typically, two memory cells 28 share an erase gate 29. Each cell 28 includes vertically stacked, self aligned floating and control gates 31 and 32. Each memory cell 28 also includes a select gate 33 positioned to one side of the stacked floating and control gates.
Source and drain diffusions 34, 36 are formed in the substrate 49, with programming paths extending from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extending from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate.
An oxide layer (not shown) is thermally grown on a monocrystalline silicon substrate 49 which is patterned with strips of field oxide or shallow trench isolation 60 parallel to bit lines 67, as shown in FIG. 1B.
The conventional split-gate memory cell offers self-aligned control gate and floating gate to reduce memory cell space and provide better programming and erasure performance. The conventional floating gate, however, is not self-aligned with shallow trench isolation (STI) and source line (SL), thus hindering further scale-down of highly integrated memory applications.